1. Technical Field
The present invention relates to a memory embedded logic semiconductor device in which a memory section and a logic circuit are integrated on the same semiconductor substrate, and a method of manufacturing the same.
2. Related Art
In memory embedded logic LSIs, a memory section and a logic circuit are integrated on the same semiconductor substrate. Since a cell area of a dynamic random access memory (DRAM) is smaller than a cell area of a static ram (SRAM), DRAM embedded logic LSIs have the advantage of being able to embed memory device of mass storage, and, on the other hand, they have a drawback that a DRAM forming process is required in addition to a process of forming the logic circuit, resulting in a high manufacturing cost. As a structure of a memory cell of the DRAM, two types of structures, called a stack type and a trench type, are known. In the trench type, a deep groove is formed in the semiconductor substrate due to etching, and capacitor materials are buried in this groove. For this reason, there is a problem that a groove having a high aspect ratio has to be formed with a high degree of accuracy, and a capacitor insulating film is required to be uniformly formed within the formed groove, which results in difficulty in thinning down.
Meanwhile, the stack type is classified into a capacitor over bitline (COB) type and a capacitor under bitline (CUB) type. The CUB type structure is a structure in which the capacitor is formed in a layer located further downward than the bit line. On the other hand, in the COB type structure, the capacitor is formed in a layer located further upward than the bit line. In general, the COB type structure has an advantage over the CUB type structure in terms of thinning. Such a COB type structure is disclosed in, for example, Japanese Unexamined Patent Publication No. 2002-353334.
Hereinafter, a DRAM embedded logic semiconductor device including the COB type structure disclosed in Japanese Unexamined Patent Publication No. 2002-353334 will be outlined. FIG. 1 is a schematic cross-sectional view of the semiconductor device. As shown in FIG. 1, the semiconductor device includes a DRAM region in which a memory cell is formed, and a logic region in which a logic circuit is formed, on the same semiconductor substrate 11. A first insulating film 19, a second insulating film 25, a third insulating film 40, a fourth insulating film 43 and a fifth insulating film 44 are sequentially stacked on the semiconductor substrate 11.
In a DRAM region, a bit line 34 is formed within a groove formed in a second insulating film 25, and a capacitor (capacitive element) 42 having a metal-insulator-metal (MIM) structure is formed in a concave portion 41 of a third insulating film 40 located further upward than the bit line 34. Contact holes 20 and 38 are respectively formed in the first insulating film 19 and the second insulating film 25, and a takeoff electrode 21 and a storage node contact plug 39 are buried within the contact holes 20 and 38. The takeoff electrode 21 and the storage node contact plug 39 electrically connect between an impurity diffusion region 13 and the capacitor 42 of a MOS transistor. Interconnect grooves 151 and 152 are formed in the fifth insulating film 44 of the uppermost layer, and interconnects 161 and 162 made of copper and the like are buried in the interconnect grooves 151 and 152. The interconnect 161 is connected to the capacitor 42 through an electrode 141.
On the other hand, contact holes 133, 134, 137, 135, and 136 passing through the second insulating film 25, the third insulating film 40 and the fourth insulating film 43 are formed in the logic regions (standard voltage logic region and high voltage logic region). Takeoff electrodes (contact plugs) 143, 144, 147, 145, and 146 are respectively buried within the contact holes 133, 134, 137, 135, and 136. In addition, takeoff electrodes (contact plugs) 59 and 69 are buried within the contact holes formed in the first insulating film 19. The takeoff electrodes 59 and 69 are connected to impurity diffusion regions (source and drain regions) 55 and 65 through a silicide film. Interconnect grooves 153, 154, 155, and 156 are formed in the fifth insulating film 44 of the uppermost layer, and metal interconnects 163, 164, 165, and 166 made of copper and the like are buried within the interconnect grooves 153, 154, 155, and 156. The takeoff electrodes 59, 69, 143 to 147 electrically connect between the metal interconnects 163 to 166 of the uppermost layer and the impurity diffusion regions (source and drain regions) 55 and 65 of the MOS transistor.
The present inventor has recognized as follows. In the COB type structure of the semiconductor device disclosed in Japanese Unexamined Patent Publication No. 2002-353334, there is a problem that the second insulating film 25 is formed on the first insulating film 19, and then the bit line 34 and the storage node contact 39 are formed in parallel in the second insulating film 25, which results in an increased number of manufacturing processes.
As described above, in the DRAM region, the contact hole 20 is formed in the first insulating film 19 in order to connect the impurity diffusion region 13 to the capacitor 42, and the contact hole 38 is formed in the second insulating film 25. The storage node contact plug 39 and the takeoff electrode 21 are stacked within these contact holes 20 and 38. Accordingly, there is a problem that the aspect ratio of the contact holes 20 and 38 is high, which causes an increase in the connection resistance between the capacitor 42 and the impurity diffusion region 13.
On the other hand, in the logic region, the takeoff electrodes 144 to 146 are formed by forming the contact holes 134 to 136 which pass through the second insulating film 25, the third insulating film 40 and the fourth insulating film 43, and burying metallic materials such as tungsten in these contact holes 134 to 136. Accordingly, there is another problem that the aspect ratio of the contact holes 134 to 136 is high, which causes an increase in the connection resistance.
In general, in the processes of manufacturing the semiconductor device, although the contact hole is formed by performing anisotropic dry etching in which a photoresist is used as a mask with respect to an insulating film, the sidewall adjacent to an opening of the formed contact hole inclines somewhat from the vertical direction. Thus, since an area of the bottom of the contact hole is smaller than an area of the opening, the contact resistance in the bottom thereof increases. Accordingly, when the aspect ratio of the contact holes 20, 38, and 134 to 136 becomes high, the connection resistance increases.
In view of such circumstances, the invention is aimed at providing a semiconductor device having a structure capable of reducing the number of manufacturing processes and realizing a low connection resistance, and a method of manufacturing the same.